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RM0008
Figure 8.
Clock tree
Low-, medium- and high-density reset and clock control (RCC)
U S B
Pre s c a ler
/1, 1.5
Peripher a l clock
en ab le
4 8 MHz
I2 S3 CLK
I2 S 2CLK
U S BCLK
to U S B interf a ce
to I2 S3
to I2 S 2
8 MHz
H S I RC
H S I
/2
Peripher a l clock
en ab le
Peripher a l clock
en ab le
Peripher a l clock
en ab le
72 MHz m a x
S DIOCLK
to S DIO
F S MCCLK
to F S MC
HCLK
to AHB bus , core,
Clock
memory a nd DMA
PLL S RC
PLLMUL
S W
/ 8
En ab le
to Cortex S y s tem timer
FCLK Cortex
peripher a l s
..., x16
x2, x 3 , x4
PLL
H S I
PLLCLK
H S E
S Y S CLK
72 MHz
m a x
AHB
Pre s c a ler
/1, 2..512
APB1
Pre s c a ler
/1, 2, 4, 8 , 16
free r u nning clock
3 6 MHz m a x PCLK1
to APB1
Peripher a l Clock
En ab le
C SS
TIM2, 3 ,4,5,6,7
If (APB1 pre s c a ler =1) x1
el s e x2
to TIM2, 3 ,4,5,6 a nd 7
TIMXCLK
Peripher a l Clock
En ab le
PLLXTPRE
APB2
Pre s c a ler
72 MHz m a x
PCLK2
O S C_OUT
4-16 MHz
/1, 2, 4, 8 , 16
Peripher a l Clock
peripher a l s to APB2
O S C_IN
H S E O S C
/2
En ab le
TIM1 & 8 timer s
If (APB2 pre s c a ler =1) x1
el s e x2
to TIM1 a nd TIM 8
TIMxCLK
Peripher a l Clock
O S C 3 2_IN
O S C 3 2_OUT
L S E O S C
3 2.76 8 kHz
/12 8
L S E
RTCCLK
to RTC
ADC
Pre s c a ler
/2, 4, 6, 8
En ab le
to ADC1, 2 or 3
ADCCLK 14 MHz m a x
RTC S EL[1:0]
/2
HCLK/2
To S DIO AHB interf a ce
MCO
L S I RC
40 kHz
M a in
Clock O u tp u t
L S I
/2
to Independent W a tchdog (IWDG)
IWDGCLK
PLLCLK
H S I
Peripher a l clock
en ab le
Le g end:
H S E = High- s peed extern a l clock s ign a l
H S I = High- s peed intern a l clock s ign a l
MCO
H S E
S Y S CLK
L S I = Low- s peed intern a l clock s ign a l
L S E = Low- s peed extern a l clock s ign a l
a i14752d
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
Doc ID 13902 Rev 9
77/995
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